For an input pulse train of clock period T, the delay produced by an n stage shift register is A. (n-l)T B. nT C. (n+l)T D. 2nT E. None of the above

(n-l)T
nT
(n+l)T
2nT E. None of the above

The correct answer is B. nT.

A shift register is a type of digital circuit that stores a sequence of bits. It is made up of a series of flip-flops, which are basic memory elements that can store a single bit. The bits are stored in the shift register in a linear fashion, with the most recent bit being stored in the first flip-flop and the oldest bit being stored in the last flip-flop.

When a clock signal is applied to the shift register, the bits are shifted one position to the right. The oldest bit is shifted out of the register and the newest bit is shifted in. The delay produced by a shift register is equal to the number of stages in the register.

For example, a 4-stage shift register will produce a delay of 4

clock cycles. This is because each bit in the register takes one clock cycle to shift to the right.

The options A, C, and D are incorrect because they do not represent the number of stages in the shift register. Option E is incorrect because it is not a valid option.